Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional TI ADC. The TI ADC 100 generally comprises a divider 102, ADCs 104-0 to 104-(M−1), and a multiplexer or mux 106. In operation, the divider 102 divides a clock signal CLK (with a frequency of FS) into M clock signals (each with a frequency of FS/M) that are staggered and provided to ADCs 104-0 to 104-(M−1). This allows each of ADCs 104-0 to 104-(M−1) to convert the analog signal X(t) to digital output signals X0(k) to XM−1(k) that can be multiplexed by mux 106 to generate a digital output signal X(k).
ADCs 104-0 to 104-(M−1), though, are not identical to each other; there are differences, which result in differences in the output signals X0(k) to XM−1(k). Accordingly, each of the output signals X0(k) to XM−1(k) can be modeled as follows:Xi(k)=GiX((kM+i)TS+δi)+DCi∀iε[0,M−1],  (1)where Gi, δi, and DCi are the gain, timing error, and DC offset for the ADC 104-i, and where TS is the period of clock signal CLK or the sampling period. Ideally, Gi, δi, and DCi are equal to 1, 0, and 0 (respectively). A difficulty in the building and operation of a TI ADC, such as TI ADC 100, is accounting for the timing error or sampling mismatches δi.
Some examples of conventional circuit are: U.S. Pat. No. 5,294,926; U.S. Pat. No. 6,542,017; U.S. Pat. No. 6,570,410; U.S. Pat. No. 6,771,203; U.S. Pat. No. 7,352,316; U.S. Pat. No. 7,501,967; U.S. Patent Pre-Grant Publ. No. 2006/0097901; U.S. Patent Pre-Grant Publ. No. 2007/0069937; Vogel, “Comprehensive Error Analysis of Combined Channel Mismatch Effects in Time-Interleaved ADCs,” Instrumentation and Measurement Technology Conference, pp. 733-738, May 20-22, 2003; Vogel et al., “Analysis and compensation of nonlinearity mismatches in time-interleaved ADC arrays,” IEEE International Symposium on Circuits and Systems, pp. 593-596, 2004; Vogel et al., “Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning,” 47th IEEE International Midwest Symposium on Circuits and Systems, pp. 1341-1344, 2004; Vogel, “A Frequency Domain Method for Blind Identification of Timing Mismatches in Time-Interleaved ADCs,” Proceedings of the IEEE Norchip Conference 2006, pp. 45-48, Nov. 20-21, 2006; Saleem et al. “LMS-Based Identification and Compensation of Timing Mismatches in a Two-Channel Time-Interleaved Analog-to-Digital Converter,” Proceedings of the IEEE Norchip Conference 2007, Nov. 19-20, 2007; Vogel et al. “Adaptive Blind Compensation of Gain and Timing Mismatches in M-Channel Time-Interleaved ADCs,” Proceedings of the 14th IEEE International Conference on Electronics, Circuits and Systems, pp. 49-52, Sep. 1-3, 2008; Vogel et al. “A Flexible and Scalable Structure to Compensate Frequency Response Mismatches in Time-Interleaved ADCs,” IEEE Transactions on Circuits and Systems I: Regular Papers, accepted for publication; and Elbornsson et al., “Blind Adaptive Equalization of Mismatch Errors in a Time-Interleaved A/D Converter System,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 151-158, Vol. 51, No. 1, January 2004.